The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 23, 2003
Filed:
Dec. 19, 2000
Mehul Vashi, Santa Clara, CA (US);
Kiran Buch, Fremont, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method and system for converting an architecture-specific design of a first type into an architecture-specific design of a second type such that race conditions and other anomalies are detected in the second type. By identifying routing delays in a first architecture and what those same routing delays would be in a second architecture, the method and system verify that a design has been properly converted. The method and system are applicable to the conversion of programmable interconnect logic devices to mask programmable logic devices. For example, a method for verifying timing for a design implemented in a new device when the design is to be moved from an old device. The method is particularly useful for verifying timing in a mask programmable device (HardWire) when the design is being converted from a field programmable device (FPGA). By identifying routing delays of critical paths and paths for which a designer has established requirements, the method efficiently and reliably determines which paths in the new device need to be compared and verified. Reports generated according to the method of the invention greatly simplify the task of assuring a satisfactory conversion.