The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2003

Filed:

Dec. 14, 2000
Applicant:
Inventors:

Subbu Ganesan, Saratoga, CA (US);

Leonid Alexander Broukhis, Fremont, CA (US);

Ramesh Narayanaswamy, Mountain View, CA (US);

Ian Michael Nixon, Sunnyvale, CA (US);

Assignee:

Tharas Systems, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/45 ;
U.S. Cl.
CPC ...
G06F 9/45 ;
Abstract

A run time controller which controls the sequence of evaluations of combinatorial blocks in a functional verification system. A target design is partitioned into multiple clusters, with each cluster in turn containing multiple combinatorial blocks. Evaluation units may be designed to evaluate the combinatorial blocks in each cluster in parallel. The run time controller may contain a flow processor, a flow control memory, and a cluster control memory. The contents of cluster control memory may be configured to specify how different condition bits/registers are to be altered upon evaluation of each cluster. The flow control memory is configured with instructions to data from different sources to be sent the evaluation units. In addition, the instructions are designed to examine the status of different registers and cause the flow processor to alter the evaluation flows.


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