The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2003

Filed:

Apr. 19, 1999
Applicant:
Inventors:

John A. Morrison, Ft. Collins, CO (US);

Michael S. Allison, Ft. Collins, CO (US);

Leo J. Embry, Ft. Collins, CO (US);

Assignee:

Hewlett-Packard Company, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/324 ; G06F 1/336 ;
U.S. Cl.
CPC ...
G06F 1/324 ; G06F 1/336 ;
Abstract

An apparatus and method for distributing interrupts to Intel® Architecture (IA)-32 processors includes a system bus having a number of nodes. Each node includes a bridge that couples the system bus to a processor bus. The processor bus may include multiple IA-32 processors. The system bus may include any number of nodes. Interrupt transactions appearing on the system bus are converted by the bridge to interrupt signals. The bridge asserts the interrupt signals at one of two pins on a target IA-32 processor. One pin may be programmed to receive non-maskable interrupts and the other pin may be programmed to receive external interrupts. The bridge incorporates a priority and threshold mechanism. The bridge includes a buffer to store pending interrupt signals. The apparatus and method may be used in a mixed IA-32 and IA-64 computer architecture that uses IA-64 components to receive interrupts and uses the bridge to convert the transactions on an IA-64 bus into interrupt signal assertions to an IA-32 processor.


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