The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 23, 2003
Filed:
Apr. 19, 1999
Akira Kubo, Himeji, JP;
Takaaki Kamimura, Himeji, JP;
Masayuki Dojo, Himeji, JP;
Kiyotsugu Mizouchi, Himeji, JP;
Masahiko Machida, Himeji, JP;
Shigeyuki Motokawa, Tokyo-to, JP;
Tomoki Miyaji, Ibo-gun, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
An object of the present invention is to simplify steps for manufacturing a matrix array substrate by reducing the number of masks being necessary to manufacture and to improve yield ratio of the matrix array substrate. According to the present invention, on a glass substrate, scanning lines, signal lines, a first insulated film, a second insulated film, an unprocessed semiconductor film, an unprocessed channel protective film, unprocessed low resistance semiconductor film, and Mo/Al/Mo laminated film are formed. Then, the source electrodes, the drain electrodes, the signal lines, a semiconductor film, and a low resistance semiconductor film are formed at a time by patterning using a common mask pattern. Display pixel electrodes cover upper surfaces of the source electrodes, the drain electrodes, the semiconductor film, the scanning line pads, and the signal line pads. Edge lines of the source electrodes, the low resistance semiconductor film, and the semiconductor film are aligned, and edge lines of the drain electrodes, the low resistance semiconductor film and the semiconductor film are aligned.