The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2003

Filed:

Jul. 20, 2000
Applicant:
Inventors:

Lorenzo Bedarida, Vimercate, IT;

Fabio Disegni, Aix en Provence, IT;

Vincenzo Dima, Monza, IT;

Simone Bartoli, Cambiago, IT;

Assignee:

STMicroelctronics S.r.l., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/704 ;
U.S. Cl.
CPC ...
H03K 1/704 ;
Abstract

A circuit design of a transistor connected as a diode, in particular to a design able to reduce the threshold voltage of the transistor and equal to the difference of the threshold voltage of the used transistors in the circuit disposal. The circuit design includes a first pMOS transistor having a second nMOS transistor connected as a diode connected between the gate and the drain of the first transistor and a current generator connected to the gates of the two transistors. Such a circuit design is also applicable to a nMOS transistor. From a general point of view the invention is directed to a nMOS or pMOS transistor whose gate voltage is increased (for the nMOS transistors) or decreased (for the pMOS transistors) by using a circuit in series with the gate that provides an appropriate delta of voltage. 3)


Find Patent Forward Citations

Loading…