High frequency field effect transistor with carrier extraction to reduce intrinsic conduction

Abstract

A field effect transistor (FET) is of the type which employs base biasing to depress the intrinsic contribution to conduction and reduce leakage current. It incorporates four successive layers ( to ): a p InSb base layer ( ), a InAlSb barrier layer ( ), a &pgr; intrinsic layer ( ) and an insulating SiO layer ( ); p source and drain regions ( ) are implanted in the intrinsic layer ( ). The FET is an enhancement mode MISFET ( ) in which biasing establishes the FET channel in the intrinsic layer ( ). The insulating layer ( ) has a substantially flat surface supporting a gate contact ( ). This avoids or reduces departures from channel straightness caused by intrusion of a gate groove, and enables a high value of current gain cut-off frequency to be obtained. In FETs with layers that are not flat, departures from channel straightness should not be more than 50 nm in extent, preferably less than 5 nm.