The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2003

Filed:

Dec. 04, 2001
Applicant:
Inventors:

Ajay Chandna, Austin, TX (US);

Tom O'Brien, Austin, TX (US);

David Lyndell Brown, Austin, TX (US);

Assignee:

PTS Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/13205 ; H01L 2/14763 ;
U.S. Cl.
CPC ...
H01L 2/13205 ; H01L 2/14763 ;
Abstract

Techniques are described for semiconductor chips with reduced capacitive power dissipation as a result of improved conductor line spacing. The approaches are particularly applicable to 0.25 micron chip design processes and below. According to one aspect, where there are n available metallization layers available to the designer, a smaller number of layers, such as n−1, are utilized initially in developing a routing design. Then, at least one further metallization layer is used to systematically route conductors, such as bus conductors, to increase the number of metal pitches between conductors, by promoting conductors from one layer to another.


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