The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 23, 2003
Filed:
Dec. 15, 2000
James Chang, Cupertino, CA (US);
Ronald T. Kaneshiro, Mountain View, CA (US);
Stefano G. Therisod, Sunnyvale, CA (US);
Agilent Technologies, Inc., Palo Alto, CA (US);
Abstract
A submount substrate is used for the dual purposes of enabling simultaneous burn-in processing for a relatively large number of arrays of optical transmitters and enabling conventional dicing techniques to be used to form mounting-ready assemblies. In the preferred embodiment, the submount substrate is a silicon wafer that is specifically designed to provide connectivity between VCSEL arrays and burn-in equipment during the testing stage, but is also designed to be segmented and used in the final packaging stage. Because the submount is a silicon wafer, conventional integrated circuit fabrication techniques may be used to form conductive patterns that define array-receiving areas and that allow external circuitry to communicate with the various VCSEL arrays.