The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2003
Filed:
Nov. 14, 2000
Applicant:
Inventors:
Assignee:
Fujitsu Limited, Kawasaki, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
A method of determining wire layouts of a circuit in a semiconductor device that includes a plurality of modules each corresponding to a circuit block includes the steps of providing module terminals of modules to be connected together in a same single layer, determining layouts of wires connected to the module terminals inside the respective modules by laying out the wires in one or more layers no higher than the single layer, and determining layouts of inter-module wires connecting between the module terminals by laying out the inter-module wires in the one or more layers no higher than the single layer.