The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2003

Filed:

Aug. 06, 2001
Applicant:
Inventors:

Ko Miyazaki, Kokubunji, JP;

Kazuhiko Eguchi, Nagoya, JP;

Tadaaki Tanimoto, Higashimurayama, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

The optimization algorithm candidate of a plurality of circuit blocks given with the logic circuit description based on the hardware description language is determined considering the Hamming distance of circuit block (S to S ). The common circuit blocks of the optimization algorithm candidate determined in the first process are then grouped considering the coupling degree among circuit blocks (S to S ). Result of grouping is the result for the circuit blocks having apparent characteristic in the algorithm candidate and coupling degree and the circuit blocks having uncertain characteristics are also left. In view of optimizing the grouping for the circuit blocks having uncertain characteristics, the grouping of a plurality of circuit blocks is optimized with the hereditary algorithm by reflecting the result of grouping on the initial condition. Thereby, the logical composition for the logic circuit description based on the hardware description language can be optimized and the necessary time can be shortened.


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