The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2003

Filed:

Jan. 03, 2000
Applicant:
Inventors:

James B. Keller, Palo Alto, CA (US);

Ramsey W. Haddad, Cupertino, CA (US);

Stephan G. Meier, Sunnyvale, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 ;
U.S. Cl.
CPC ...
G06F 9/38 ;
Abstract

A scheduler issues memory operations without regard to whether or not resources are available to handle each possible execution outcome of that memory operation. The scheduler also retains the memory operation after issuance. If a condition occurs which prevents correct execution of the memory operation, the memory operation is retried. The scheduler subsequently reschedules and reissues the memory operation in response to the retry. Additionally, the scheduler may receive a retry type indicating the reason for retry. Certain retry types may indicate a delayed reissuance of the memory operation until the occurrence of a subsequent event. In response to such retry types, the scheduler monitors for the subsequent event and delays reissuance until the event is detected. The scheduler may include a physical address buffer to detect a load memory operation which incorrectly issued prior to an older store memory operation upon which it is dependent for the memory operation. The scheduler may also include a store tag buffer to detect that a load memory operation is to be reissued due to the reissuance of a store memory operation on which the load was determined to be dependent during the previous execution of the load memory operation.


Find Patent Forward Citations

Keller, James. (2003). Scheduler which retries load/store hit situations (U.S. Patent No. 6622235). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6622235

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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