High speed, low power switched-capacitor digital-to-analog converter with a precharge arrangement

Abstract

A switched capacitor digital-to-analog converter includes a first voltage generator for providing first and second reference voltages, a second voltage generator for providing third and fourth reference voltages selected to match predetermined design values of the first and second reference voltages, and an array of binary weighted capacitors. Each capacitor has a first electrode connected to a common circuit node, which is connected to a converter output terminal and a second electrode selectively connected, through an associated first switching circuit, to either one of the first and second reference voltages or, through an associated second switching circuit, to either one of the third and fourth reference voltages. The converter includes a circuit for monitoring the values of each bit of input digital codes, and a control circuit coupled to the first and second switching circuits to open or close selectively during a bit clock period the connections to the first, second, third, and fourth voltages according to the following criterion: when a bit value of the current input digital code B is equal to the corresponding bit value of the previous input digital code B , the first switching circuit is enabled and the second switching circuit is disabled during the whole bit clock period, and when the monitoring circuit detects a bit value of a current input digital code B to be different from the corresponding bit value of the previous input digital code B , the first switching circuit is disabled and the second switching circuit is enabled during a starting time portion of the bit clock period, while the first switching circuit is enabled and the second switching circuit is disabled during the remaining portion of the bit clock period.