The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2003
Filed:
Nov. 07, 2001
Allan L. Mullgrav, Jr., Wappingers Falls, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A power supply noise compensation amplifier has an input for connection to a power supply. The amplifier includes a differential amplifier circuit for providing an instantaneous amplified signal in response to power supply noise, and produces an output signal with an instantaneous opposite polarity from the power supply noise so a noise sensitive circuit connected to the noise compensation amplifier has a compensated power supply signal which enables it to produce a reduction in the amplitude of the noise signal at the output thereof. The differential amplifier circuit includes a differential pair of coupled transistor circuits including a leading transistor circuit and a lagging transistor circuit. The leading and lagging transistor circuits have source-drain circuits connected in parallel to the source-drain circuit of a constant current transistor so the leading and lagging transistor circuits must share a common current as a function of voltages on the leading node connected to the gate of the leading transistor and a lagging node connected to the gate of the lagging transistor. The leading transistor circuit includes a first FET transistor having leading node connected to both and the gate electrode thereof and a resistive circuit. The lagging transistor circuit includes a lagging FET transistor having a lagging node connected to both the gate electrode thereof and the resistive and capacitive elements, and the differential amplifier circuit includes a differential pair of coupled transistor circuits including a leading transistor circuit and a lagging transistor circuit.