The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2003
Filed:
Sep. 14, 2001
Charles E. May, Gresham, OR (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A dual-damascene process for forming an integrated circuit structure is described. The process includes forming a trench in a dielectric substrate, and forming a via mask layer over the dielectric substrate and the trench. An aperture is formed in the via mask layer overlying the trench, thereby exposing a portion of the underlying dielectric substrate. The exposed portion of the dielectric substrate is subjected to an ion beam to damage the exposed dielectric material. The damaged portion of the dielectric substrate is then removed, such as by etching, thereby forming a via cavity below the trench in the dielectric substrate. Generally, the damaged portion of the dielectric substrate etches at a faster rate than do adjacent non-damaged regions. With a faster etch, there is practically no outward spreading of the via cavity as the etch proceeds downward through the dielectric substrate, thereby forming a via cavity wall that is very nearly vertical. More precise control of via cavity geometry provides for more precise alignment of the via cavity with underlying conductors in the integrated circuit structure.