Manufacture of trench-gate semiconductor devices

Abstract

A vertical power transistor trench-gate semiconductor device has an active area ( ) accommodating transistor cells and an inactive area ( ) accommodating a gate electrode ( ) (FIG. ). While an n-type layer ( ) suitable for drain regions still extends to the semiconductor body surface ( ), gate material ( ) is deposited in silicon dioxide insulated ( ) trenches ( ) and planarised to the top of the trenches ( ) in the active ( ) and inactive ( ) areas. Implantation steps then provide p-type channel-accommodating body regions ( A) in the active area ( ) and p-type regions ( B) in the inactive area ( ), and then source regions ( ) in the active area ( ). Further gate material ( ) is then provided extending from the gate material ( ) in the inactive area ( ) and onto a top surface insulating layer ( B) for contact with the gate electrode ( ). The channel profiles of the device are optimised by providing the p-type regions ( A) after the trench insulation ( ), and voltage breakdown at the bottom corners of the trenches ( ) is suppressed by providing the p-type regions ( B) in the inactive area ( ).