The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2003

Filed:

Aug. 21, 2000
Applicant:
Inventor:

Peter Pöchmüller, München, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

A configuration for producing test signals for testing semiconductor chips includes a clock signal source for producing a clock signal, and a tester. The test signals are produced on the respective semiconductor chips in a precise temporal sequence with respect to the clock signal. The temporal sequence of the test signals on a respective one of the semiconductor chips is determined from the clock signal. Latches are connected downstream of each of the signal inputs for each of the test signals. A DLL unit uses the clock signal to produce a delayed clock signal to activate the latches. Switches to be driven by a test mode signal are disposed in parallel with the latches. A method for producing test signals for testing semiconductor chips includes the steps of supplying test signals to semiconductor chips in a precise temporal sequence with respect to a clock signal, and determining from the clock signal the temporal sequence of the test signals on each of the semiconductor chips.


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