System for compensating delay of high-speed data by equalizing and determining the total phase-shift of data relative to the phase of clock signal transmitted via separate path

Abstract

Method and circuitry for determining the timing of data arriving to a predetermined point via a data-bus from two or more data sources located at different locations along the data-bus. The timing is initiated by a first clock signal selected from a plurality of clock signals, at a frequency that is transmitted from a first clock generator. For each data source, the total phase-shift of the data relative is equalized to the phase of the transmitted first clock signal. The total phase-shift is determined by transmitting a first clock signal via a separate transmission path and receiving it at the end of the path. The determined total phase-shift is then utilized for enabling data reading.