The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2003

Filed:

Oct. 21, 1999
Applicant:
Inventor:

Richard Lansdowne, Southampton, GB;

Assignee:

Semtech Corporation, Newbury Park, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 7/00 ;
U.S. Cl.
CPC ...
H04L 7/00 ;
Abstract

An asynchronous timing oscillator re-synchronizer enables a clocked system which uses a high frequency clock to measure time intervals to re-synchronize to the clock after it has been temporarily disabled, using a low frequency, low accuracy, low power clock to determine the number of high frequency clock cycles that would have occurred during such intervals. Both high frequency and low frequency clocks are provided to the re-synchronizer, and the ratio between their respective frequencies is periodically determined and stored. A command sent to the re-synchronizer disables the high frequency clock for a specified number of cycles of the low frequency clock. When the disablement period has expired, the high frequency clock is re-enabled. While the high frequency clock is disabled, a register is periodically incremented by the stored clock ratio, such that when the high frequency clock is re-enabled, the number in the register represents the number of high frequency clock cycles that would have occurred during the disablement period. This number is provided to the clocked system to re-synchronize the clocked system to the high frequency clock.


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