The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2003
Filed:
Mar. 06, 2001
Applicant:
Inventors:
Robert J. Blakely, Ft. Collins, CO (US);
John S. Atkinson, Fort Collins, CO (US);
Assignee:
Hewlett-Packard Development Company, L.P., Houston, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/18 ; H05K 1/03 ; H05K 1/16 ; H01G 4/228 ;
U.S. Cl.
CPC ...
H05K 1/18 ; H05K 1/03 ; H05K 1/16 ; H01G 4/228 ;
Abstract
A capacitor mounting method and resulting printed circuit board that increases the mounting density of both vias and decoupling capacitors is presented. Vias are shared between capacitors mounted on the top and bottom of the printed circuit board. This arrangement allows increased decoupling capacitor density and avoids the current doubling problem when shared vias are connected with capacitors installed on the same side of the board.
Quick Actions:
Blakely, Robert. (2003). Method for high-density, low-via-count, decoupling capacitor placement (U.S. Patent No. 6618266). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6618266
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile