The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2003

Filed:

Dec. 09, 2002
Applicant:
Inventor:

Satoshi Sakurai, San Diego, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 1/38 ;
U.S. Cl.
CPC ...
H03M 1/38 ;
Abstract

A method and apparatus are arranged for minimizing the effects of capacitor mismatch errors in pipelined analog-to-digital converters (ADC). The virtual elimination of capacitor mismatch effects is achieved without trading comparator-offset margin by an appropriate selection of comparator circuits' reference signals and the inclusion of a plurality of capacitors that are switched into an appropriate feedback position. The appropriate feedback position in the switched capacitor amplifier circuit is determined based on the operating region. For each of k pipeline stage, a method includes: determining an operating region of a sampled analog input signal for a predetermined transfer curve, and computing digital code bits and an improved residue signal for this stage based on the determined operating region, and then computing a final conversion code from the digital code bits of the k pipeline stages.


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