Circuits and methods for generating internal clock signal of intermediate phase relative to external clock

Abstract

A circuit includes a clock buffer to generate an initial reference clock signal responsive to an external clock signal, a DMC to receive the initial reference clock signal, and an array of forward units to receive a signal from the DMC. The circuit also includes an array of back units that produces a back signal. The back signal is input in a clock driver to produce an internal clock signal. A delay element produces a delayed reference signal responsive to the initial reference clock signal. A plurality of MCCs receive an output of one of the forward units and the delayed reference clock signal. When one of the outputs of the forward units is synchronized with the delayed reference clock signal, one of the back units is thereby activated, which initiates generation of the back signal.