The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2003
Filed:
Feb. 01, 2002
Applicant:
Inventor:
Goran Bilski, San Jose, CA (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/9177 ;
U.S. Cl.
CPC ...
H03K 1/9177 ;
Abstract
Structures and methods that reduce interconnect resource usage and routing delays in FPGAs by routing high fan-out signals on the CLB carry chains. In a first embodiment, a high fan-out signal distribution structure is implemented in a Field Programmable Gate Array (FPGA). The FPGA includes an array of logic cells, each including a carry multiplexer. The carry multiplexers can be configured to form a carry chain. The carry chain is used to distribute high fan-out signals by passing a high fan-out signal along the chain from carry-in terminal to carry-out terminal, and tapping the signal at the carry-out terminals for distribution to a large number of destinations.