The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2003

Filed:

Feb. 20, 2002
Applicant:
Inventor:

Sung Gyu Pyo, Kyungki-Do, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/14763 ;
U.S. Cl.
CPC ...
H01L 2/14763 ;
Abstract

A method of manufacturing a metal wiring in a semiconductor device is disclosed. The method comprises forming a photosensitive film so that an underlying metal wiring can be exposed, adhering an chemical enhancer only to the underlying metal wiring, depositing a metal layer by CECVD method so that the metal layer is selectively deposited at the portion in which the chemical enhancer is formed, removing the photosensitive film and chemical enhancer, and forming a diffusion barrier layer spacer at the sidewall of the metal layer to form an upper metal wiring. Therefore, the disclosed method can solve poor contact with an underlying metal wiring due to shortage of processional margin in the process of forming an upper metal wiring in a high integration semiconductor device.


Find Patent Forward Citations

Pyo, Sung. (2003). Method of manufacturing a metal wiring in a semiconductor device (U.S. Patent No. 6617238). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6617238

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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