The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2003

Filed:

Oct. 05, 2000
Applicant:
Inventors:

Yamazaki Toshio, Ogo-ri, JP;

Fukutomi Naoki, Tokyo, JP;

Suzuki Kazuhisa, Nagareyama, JP;

Morita Hiroshi, Fujisawa, JP;

Wakashima Yoshiaki, Kawasaki, JP;

Naoyuki Susumu, Yuki, JP;

Kida Akinari, Shimotsuga, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/144 ;
U.S. Cl.
CPC ...
H01L 2/144 ;
Abstract

A semiconductor device comprising a substrate with a cavity portion for mounting a semiconductor chip is provided to achieve a high reliability and to decrease a size and a fabricating cost. The cavity portion for mounting the semiconductor chip at the center portion of the substrate is formed by press forming with a projected portion of a die while adhering a press shapeable wiring body comprising a copper wiring which becomes wiring material, a barrier layer such as nickel alloy or the like, and a copper foil which is a carrier layer, to a resin substrate, so as to have wiring buried into a surface of the substrate and to form a ramp between an inner connection terminal portion connecting to the semiconductor chip and an external connection terminal portion connecting to an external connection terminals, the internal and external connection terminal portions being two end portions of the wiring.


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