Method for handling coupling effects in static timing analysis

Abstract

A method for performing a static timing analysis on an integrated circuit chip or module taking into account the effect of wiring interconnection coupling is described. The wiring interactions are modeled as appropriate equivalent grounded capacitances, allowing traditional delay calculation methods to be applied. The method includes the steps of assigning a pessimistic value to the wiring coupling interaction between nets forming the integrated circuit chip; performing the static timing analysis using computed timing parameters which are a function of net capacitance, the net capacitance being based on the pessimistic value of the coupling interaction between the nets; updating the net capacitance of selected nets based on 1) an overlap between an arrival time window of each of the selected nets and a possible arrival time window of each of the other nets which are coupled to the each of selected nets, and 2) on the slew of each of the selected nets and the slew of each of the other nets which are coupled to the selected nets; and updating the static timing analysis based on the updated net capacitances of the selected nets.