The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2003
Filed:
Mar. 01, 2002
Brian L. Brown, Allen, TX (US);
Jackson Leung, Sugar Land, TX (US);
Ronald J. Syzdek, Sugar Land, TX (US);
Pow Cheah Chang, Singapore, SG;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A semiconductor memory device ( ) having a parallel test circuit is disclosed. A test data path ( ) receives parallel I/O line (I/O -I/O ) values, and generates therefrom test result data values (PASS and DATA_TST). The test result data values (PASS and DATA_TST) are coupled to a gate control circuit ( ). The gate control circuit ( ) provides either a first logic value, a second logic value, or an intermediate logic value to an open drain output driver ( ) depending upon the test result data values (PASS and DATA_TST). In response to the logic values received from the gate control circuit ( ), the open drain output driver ( ) drives a data output (DQ) to a first, second or intermediate logic level.