Low power path memory for viterbi decoders

Abstract

A path memory for a Viterbi decoder stores 2 path select command signals generated a T interval earlier than reference clock timing. In response to a path select command signal that is generated at the reference clock timing corresponding to each of the 2 rows, one of the stored path select command signals which correspond to two possible states of a 2T interval earlier than the reference clock timing and are separated from each other by a distance of 2 rows, is selected for each row. A matrix array of memory cells are arranged in the 2 rows. To achieve low power consumption, the memory, cells are divided into a first array of odd-numbered columns and a second array of even-numbered columns. Each row of the first-array memory cells is responsive to the row-corresponding path select command signal and the selected path select command signal for selecting one of four possible states latched in the memory cells of preceding odd-numbered columns a 2T interval earlier than the reference clock timing, and each row of the second-array memory cells is responsive to the row-corresponding path select command signal and the selected path select command signal for selecting one of four possible states latched in the memory cells of preceding even-numbered columns a 2T interval earlier than the reference clock timing. The first and second arrays alternately operate at 2T-intervals.