Phase locked-loop using sub-sampling

Abstract

A PLL-based frequency synthesizer is provided. In accordance with one aspect, a phase locked loop is provided that comprises a phase detector, a loop filter, a voltage controlled oscillator, and a feedback circuit. The phase detector has as inputs a reference frequency signal and a feedback signal. The phase detector is operable to generate a phase detection signal based on a comparison of phases between the reference frequency signal and the feedback signal. The loop filter is coupled to the phase detector for receiving the phase detection signal and generates an output voltage in response to the phase detection signal. The voltage controlled oscillator is coupled to the output voltage of the loop filter and generates a local oscillator signal. The feedback circuit is coupled to the local oscillator signal and generates the feedback signal. The feedback circuit comprises a sampling circuit. The sampling circuit is operable to sample the local oscillator signal with a sampling frequency that is substantially less than the frequency of the local oscillator signal to generate a sampling circuit output signal. The sampling circuit output signal comprises a beat frequency signal having a beat frequency that is equal to the frequency difference between the frequency of the local oscillator signal and the nearest harmonic of the sampling frequency. The feedback signal is derived from the beat frequency signal.