Phase-shift-resistant, frequency variable clock generator

Abstract

A clock generator includes a frequency divider for outputting a divided clock signal by dividing an input clock signal in accordance with a dividing ratio control signal; and a phase adjusting circuit for adjusting a phase of an internal clock signal with that of an external clock signal. The frequency divider further includes a dividing ratio control signal inhibiting circuit for disabling the dividing ratio control signal as long as a lock signal supplied from the phase adjusting circuit is active. The frequency divider generates a particular clock signal as long as the dividing ratio control signal is disabled, and changes the frequency of the divided clock signal by enabling the dividing ratio control signal in synchronism with the particular clock signal when the lock signal is made inactive. The period of the particular clock signal is preferably set at a value greater than a phase adjustable range of the internal clock signal by the phase adjusting circuit, and particularly at a value equal to the longest period of the divided clock signals generated by the frequency divider. This makes it possible to prevent frequency shift involved in frequency switching in a conventional clock generator, and to save power.