Adaptive drive circuit for zero-voltage and low-voltage switches

Abstract

A circuit for controlling the switching behavior of a field effect transistor (FET) or other power switch in a power supply or converter. The circuit includes an adaptive feedback loop which controls the switching operation of the FET through application of a gate drive signal to the device. The circuit is designed to turn the switching device on or off at the optimum time to reduce the stress and power losses associated with the switching action. The circuit includes a capacitor connected to the FET switch drain to sense the falling voltage across the switch. The adaptive gate drive circuit holds the FET switch off until the drain voltage sensed by the capacitor stops decreasing. At this time, the FET switch voltage is either zero (zero-voltage switching) or has reached the minimum value of its resonant ring (low-voltage switching). The gate drive circuit then turns the FET switch on, initiating a new cycle of charging up the inductor or primary transformer winding which is part of the power supply or converter. The present invention, thus acts, to minimize switching stress and power loss during the switching cycle.