The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2003
Filed:
Feb. 05, 2002
Seungyoon P. Song, East Palo Alto, CA (US);
Elan Research, Mt. View, CA (US);
Abstract
Dynamic PLAs are used as the basis of constructing a new class of programmable devices called field-programmable dynamic logic arrays (FPDLAs). Unlike existing programmable devices that use static logic, the FPDLAs use reprogrammable, reconfigurable, and fixed-function dynamic PLAs in programmable modules that provide both programmable logic and interconnect structures. A system of micro clocks is used to ensure that each dynamic PLA operates correctly by allowing it to start the evaluate phase after all of its inputs have become valid. Since dynamic PLAs with large number of inputs can be built in a small area due to its regular circuit structure, and they produce the outputs in a time independent of the number of inputs affecting the outputs, FPDLAs can operate at a higher speed and require a smaller area than programmable devices built using static logic.