The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2003
Filed:
Jul. 10, 2000
Ryan T. Hirose, Colorado Springs, CO (US);
Loren T. Lancaster, Colorado Springs, CO (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A NAND stack array ( ) is placed within a well formed on a semiconductor substrate and includes a series array of memory cell transistors ( ) whose threshold voltages can be electrically altered over a range of depletion values. When a cell within a certain NAND stack is selected for a read operation, a peripheral circuit drives selected gate word line to the well potential and drives the word lines of the other gates within the selected NAND stack to a potential at least equal in magnitude to the magnitude of the a reference voltage plus the threshold voltage of a memory cell in the programmed state.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile