The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2003
Filed:
Sep. 12, 2001
Applicant:
Inventors:
Wolfgang Angermann, Seeshaupt, DE;
Andreas Bänisch, München, DE;
Assignee:
Infineon Technologies AG, Munich, DE;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/100 ; H01L 2/184 ; H01L 2/1336 ; H01L 2/13203 ; H01L 2/14763 ;
U.S. Cl.
CPC ...
H01L 2/100 ; H01L 2/184 ; H01L 2/1336 ; H01L 2/13203 ; H01L 2/14763 ;
Abstract
A method for fabricating a field-effect transistor situated within an integrated semiconductor circuit. At least two gate regions each extending between a source region and a drain region and are disposed such that they lie one above the other in a thickness direction of a substrate, thereby reducing the space requirement of the hitherto customary larger field-effect transistors in integrated semiconductor circuits.
Angermann, Wolfgang. (2003). Method for fabricating field-effect transistors in integrated semiconductor circuits and integrated semiconductor circuit fabricated with a field-effect transistor of this type including a dual gate (U.S. Patent No. 6613616). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6613616
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile