Method and system for efficiently testing circuitry

Abstract

A method and system for efficiently testing circuitry. The method and system may be applied to testing embedded memory circuit blocks within a programmable logic device (PLD). Circuitry used in the testing process can be implemented from the programmable logic resources of the PLD, or alternatively, could be provided as specialized, dedicated test mode circuitry. The PLD may contain an arbitrary number, n, of memory blocks with each block having an arbitrary number, x, of output pins. An AND-tree circuit is implemented that receives each of the n*x output pins. If any pin is low, the output of the AND-tree is low, otherwise, the output is high. The output of the AND-tree is an input/output pin of the PLD. An OR-tree circuit is implemented that receives each of the n*x output pins. If any pin is high, the output of the OR-tree is high, otherwise, the output is low. The output of the OR-tree is another input/output pin of the PLD. The OR-tree and AND-tree circuits can be used to detect any manufacturing faults within the PLD and can also be used to measure the max/min delay timing of the memory block signals. During testing, predetermined patterns of logic are loaded into the memory blocks and read back in predetermined sequences using the AND-tree and OR-tree results. Using this method and system, a tester can be used that has reduced pin count and parallel testing can be performed.