The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 2003
Filed:
Jan. 24, 2002
Dana How, Palo Alto, CA (US);
Adi Srinivasan, Fremont, CA (US);
Robert Osann, Jr., Los Altos, CA (US);
Shridhar Mukund, Santa Clara, CA (US);
LightSpeed Semiconductor Corporation, Sunnyvale, CA (US);
Abstract
A system for testing an integrated circuit, and particularly a gate array, is disclosed which includes, prior to coupling the array to form a user-designed circuit, predesigned logic that enables testing of the user-designed circuit. The predesigned logic allows logic blocks in the array to operate in “freeze” mode or to operate in normal mode, where normal mode is defined by the user-designed circuit. When the logic blocks are selected to be frozen, the logic blocks behave as a series of daisy-chained master-slave flip-flops. In normal mode, a logic block can implement combinational, sequential, or other functions and still later be as a master-slave flip-flop. Moreover, each logic block is further equipped for addressable mode control, allowing selected logic blocks to be exercised in isolation once stimulus data is shifted in, simplifying test generation and improving fault coverage.