Asynchronous fifo memory having built-in self test logic

Abstract

An asynchronous First-In-First-Out memory integrated circuit is equipped with a Built-In Self Test logic structure which allows extensive full-frequency asynchronous memory testing requiring minimal external test equipment. Memory input data patterns are generated by write data pattern circuitry responsive to a write clock signal. The write data generator considers the full status of the FIFO memory device. A read data generator provides an expected output data pattern corresponding to the data pattern provided by the write data generator responsive to a read clock signal such that the status of the FIFO memory device is taken into account. A read data error circuit compares the expected output data with the actual output data, indicating any mismatch between the two. Further this asynchronous First-In-First-Out memory device stores information regarding the nature of any mismatches and allows this information to be serially read from its output.