Method and system using a common reset and a slower reset clock

Abstract

The operability and scaleability of electronic circuits is improved using a circuit arrangement that is modular, scaleable, straightforward to implement and allows for simple and safe physical design implementation. According to one example embodiment of the present invention, a reset method and system are used to effect a reset at several peripheral devices that may employ similar and/or different reset strategies. A reset module is coupled to a clock module having an external clock reference and to each of the peripheral devices. Operationally, the clock module provides a functional clock signal to each of the peripheral devices at one of a plurality of first frequencies. The reset module generates an internal reset signal in response to a system reset signal. In response to an internal reset signal, the clock module drives a common reset clock signal, having a reset clock frequency, to each of the peripheral devices via clock outputs at the clock module. The reset clock frequency is equal to or slower than the functional clock frequency provided to each of the peripheral devices. A synchronization module at each of the peripheral devices is adapted to synchronize the reset signal among all peripheral devices using the reset clock signal. The reset module holds the internal reset signal for a selected amount of time, and then releases the clock module from the reset clock signal. The resets are then simultaneously released at each of the peripheral devices, making possible a smooth transition from reset.