The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2003

Filed:

Feb. 27, 2002
Applicant:
Inventor:

Yasuaki Hirano, Tenri, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract

A p-MOS transistor is connected to an intermediate node . A level shifter supplies an output signal hresetb to a gate of the p-MOS transistor based on a signal Reset. Then, in an initial state until a pump operation is started, the signal Reset is set at “H” to turn on the p-MOS transistor . Thus, a positive charge of the intermediate node is discharged via the p-MOS transistor and a negative charge is discharged via an N-well of the p-MOS transistor so that the potential of the intermediate node becomes about 0.7 V. Therefore, even when the pump operation is started and the p-MOS transistor is turned off, the maximum voltage applied to each of the capacitors C , C is 4 V, and exceeding of the withstand voltage of a capacitor insulating film can be prevented.


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