The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2003

Filed:

Mar. 18, 2002
Applicant:
Inventors:

Anilkumar C. Bhatt, Johnson City, NY (US);

Ashwinkumar C. Bhatt, Endicott, NY (US);

Subahu D. Desai, Vestal, NY (US);

John M. Lauffer, Waverly, NY (US);

Voya R. Markovich, Endwell, NY (US);

Thomas R. Miller, Endwell, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 7/16 ; H05K 1/14 ; H05K 7/10 ; H05K 1/00 ; H01R 1/204 ;
U.S. Cl.
CPC ...
H05K 7/16 ; H05K 1/14 ; H05K 7/10 ; H05K 1/00 ; H01R 1/204 ;
Abstract

Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.


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