The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 2003
Filed:
Oct. 19, 2000
Delay locked loop, synchronizing method for the same and semiconductor device equipped with the same
Misao Suzuki, Tokyo, JP;
Other;
Abstract
The delay locked operation is intermittently conducted only when a command or signal is supplied from outside, and a delay time changed in the delay locked operation is retained thereafter in the period that the command or signal is not supplied. Also, the dummy pattern used in conducting the phase comparison between internal clock ICK and external clock ECK is obtained through the output circuit that has the same characteristics as the output circuit from which data are actually output. Therefore, the accurate coincidence between internal clock ICK and external clock ECK can be obtained regardless of the parasitic inductive and capacitive loads that are influenced depending on the characteristic of package and the mounting conditions. Thereby, the delay locked operation can be always conducted accurately.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile