The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 2003
Filed:
Aug. 30, 2002
Arnold Chow, Sunnyvale, CA (US);
Kwong Shing Lin, Sunnyvale, CA (US);
Pericom Semiconductor Corp., San Jose, CA (US);
Abstract
A bus switch has an n-channel bus-switch transistor between two buses and a p-channel pullup transistor. When power is disconnected from the bus switch, and one bus is hot and has a voltage above ground, this higher voltage is conducted to the gate and substrate of the p-channel pullup transistor. This biasing keeps the p-channel transistor turned off. When power is off, a connecting p-channel transistor connects the higher voltage on the hot bus to the p-channel gate node, while an inverting p-channel transistor connects the gate node to the substrate under the p-channel transistor. Inverting transistors receive an inverse enable signal and drive the gate node when power is applied, turning on the pullup transistor when the n-channel bus-switch transistor is off, and vice-versa. The gate node is fed back and applied to the gate of a source transistor that connects power to the substrate.