The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 2003
Filed:
Jan. 28, 2002
Shiuh-Hui Steven Chen, Lake Zurich, IL (US);
Raymond Garza, Huntley, IL (US);
Carl Ross, Mundelein, IL (US);
Stefan Turalski, Chicago, IL (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A semiconductor wafer ( ) that includes a support body ( ), at least one thin die ( ), and a plurality of tethers ( ). The support body ( ) is made of a semiconductor material. The thin die ( ) has a circuit ( ) formed thereon and has an outer perimeter ( ) defined by an open trench ( ). The open trench ( ) separates the thin die ( ) from the support body ( ). The tethers ( ) extend across the open trench ( ) and between the support body ( ) and the thin die ( ). A method of making a thin die ( ) on a wafer ( ) where the wafer ( ) has a support body ( ), a topside ( ) and a backside ( ). A circuit ( ) is formed on the topside ( ) of the wafer ( ). The method may include the steps of: forming a cavity ( ) on the backside ( ) of the wafer ( ) beneath the circuit ( ) that defines a first layer ( ) that includes the circuit ( ); forming a trench ( ) around the circuit ( ) on the topside ( ) of the wafer ( ) that defines an outer perimeter ( ) of the thin die ( ); forming a plurality of tethers ( ) that extend across the trench ( ) and between the wafer support body ( ) and the thin die ( ); and removing a portion of the first layer ( ) to define the bottom surface ( ) of the thin die ( ).