The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2003

Filed:

Feb. 19, 2002
Applicant:
Inventors:

Ryuji Ariyoshi, Chiba, JP;

Isamu Kuno, Chiba, JP;

Takahito Fukushima, Chiba, JP;

Junji Aoike, Chiba, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/976 ;
U.S. Cl.
CPC ...
H01L 2/976 ;
Abstract

A semiconductor integrated contains a first MOS transistor of a first conductivity type formed on a surface of a semiconductor substrate, and a second MOS transistor of the first conductivity type having a drain-source breakdown voltage lower than that of the first MOS transistor. The second MOS transistor is used as an anti-fuse, which can be changed to a conductive state with a low writing voltage that does not damage the first MOS transistor. The second MOS transistor is fabricated such that a concentration of a second conductivity type impurity in at least a portion of the channel region adjacent to the drain region is higher than that in a corresponding portion of the first MOS transistor.


Find Patent Forward Citations

Ariyoshi, Ryuji. (2003). Semiconductor integrated circuit having anti-fuse, method of fabricating, and method of writing data in the same (U.S. Patent No. 6608355). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6608355

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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