The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2003

Filed:

Apr. 25, 2000
Applicant:
Inventors:

Duanyi Wang, Princeton, NJ (US);

Hisashi Kobayashi, Princeton, NJ (US);

Jay Bao, Bridgewater, NJ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/345 ;
U.S. Cl.
CPC ...
H03M 1/345 ;
Abstract

A matrix transform method and circuit provides for MAP decoding of turbo codes. The method begins by initializing a forward recursion probability function vector &agr; , and a backward recursion probability function vector &bgr; . Then, transition probability matrices &Ggr;(R ) and &Ggr; (R ) are determined according to each received symbol of the sequence R . And then, values of &agr; , corresponding to the received R are determined according to &Ggr;(R ). At the same time of determining &agr; , a plurality of multiplacation on &Ggr;(R ) and &Ggr; (R ) are accomplished in parallel. By making use of the results of the matrix multiplications, after receiving the complete symbol sequence R , values of all of the backward recursion probability vector &bgr; , where k=1, 2, . . . , N−1, are determined in parallel, and the log likelihood ratio for every decoded bit d , k=1, 2, . . . , N, are also determined in parallel. The circuit performs successive decoding procedures in parallel using a set of regular matrix operations. These operations substantially accelerate the decoding speed and reduce the computational complexity, and are particularly suited for implementation in special-purpose parallel processing VLSI hardware architectures. Using shift registers, the VLSI implementation effectively reduces memory requirements and simplifies complicated data accesses and transfers.


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