Neural network integrated circuit with fewer pins

Abstract

A neural network integrated circuit comprises many neuron circuits each with a distance resister that is compared in a competition for the closest-hit with all the other neurons. Such closest-hit comparison is conducted bit-by-bit over the many bit positions of a distance measure in binary format each time after the neurons fire. A single-wire AND-bus interconnects every neuron in a whole system. Each neuron drives the single-wire AND-bus with an open-collector buffer. All neurons press the single-wire AND-bus with their respective distance measures in successive cycles, starting with the most significant bit. For example, a fourteen-bit binary distance word requires fourteen comparison cycles. Any neuron that sees a “0” on the single-wire AND-bus when its own corresponding bit in its distance measure is a “1”, automatically drops from the competition. By the time the least significant bit cycle is run, a single closest distance will have been determined. Such neuron that wins announces itself with an identifying code.