The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2003

Filed:

Apr. 14, 1999
Applicant:
Inventors:

Nevine Nassif, Arlington, MA (US);

Madhav Desai, Powai, IN;

Dale Hayward Hall, Northborough, MA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/750 ; G06F 9/45 ;
U.S. Cl.
CPC ...
G06F 1/750 ; G06F 9/45 ;
Abstract

A system for rapidly accurate Elmore delays is disclosed which uses circuit simulations with different circuit configurations to generate Elmore delay models. From data generated by the simulations, Elmore delays are represented as functions of a capacitance charge and device width for a variety of device configurations. Similarly, accurate capacitance models are determined for each device. To determine an Elmore delay for a discharge path, the appropriate models are applied to each device and summed together. Within a timing verifier, the present invention can rapidly determine critical paths which require additional consideration.


Find Patent Forward Citations

Nassif, Nevine. (2003). Method and apparatus for estimating elmore delays within circuit designs (U.S. Patent No. 6606587). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6606587

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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