Multiple data rate bit synchronizer having phase/frequency detector gain constant proportional to pll clock divider ratio

Abstract

The bandwidth of a 'single loop' bit synchronizer is maintained constant over a relatively wide baud rate range, by making the loop's phase/frequency detector gain constant proportional to the loop's clock divider ratio. The phase/frequency detector may include charge pump that charges a capacitor with a current representative of the phase/frequency difference between an input data signal and the clock signal produced by the loop's clock divider. By resistor-coupling the loop filter to the capacitor, the loop filter sees a voltage that is proportional to the integral of the phase/frequency detector's output current over the symbol period of the received data signal. Since the data symbol period is the inverse of the data rate, and corresponds to the ratio of the clock frequency divisor N to the fixed output frequency produced by the VCO, the gain constant of the phase detector is proportional to the clock divisor N. Since loop bandwidth is defined in accordance with the ratio of the phase detector gain constant (which is proportional to N) to the clock divisor N, the contribution of the clock frequency divisor N is canceled, so that the loop bandwidth can be maintained constant regardless of data rate (which sets N).