The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 12, 2003
Filed:
Sep. 05, 2001
Donald M. Archer, Santa Clara, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A trim bit circuit is provided that uses a cascoded differential PMOS EPROM with a fixed offset cross-coupled latch. The output sense signal is transferred by transmission gates to NMOS latched inverters. The output is buffered by another inventor. Programming is performed by a NMOS current sink that pulls the drain of the programmed (trimmed) PMOS EPROM device to ground. This places the full positive supply across the short channel trimmed device, the punchthrough inducing a trapped charge on the device. The reference (untrimmed) PMOS EPROM device is uncharged. Thus, the two PMOS EPROM transistors have unequal current. During the read mode, a replication bias voltage is induced by an external “read” power-on-reset circuit, thereby placing a few volts below positive supply on the gates of the cascode devices. This allows the Vds of the PMOS EPROM devices to increase to a little less than a volt. Since the trimmed transistor has more current than the un-trimmed transistor by a few decades of current, the drain of the load latch transistor rises to a voltage limited by the saturation voltage of the EPROM devices, causing the output of the load latch device to be high.