The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2003

Filed:

Feb. 07, 2002
Applicant:
Inventors:

Rob Van Dalen, Eindhoven, NL;

Christelle Rochefort, Haasrode, BE;

Godefridus A. M. Hurkx, Best, NL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/9414 ; H01L 2/943 ;
U.S. Cl.
CPC ...
H01L 2/9414 ; H01L 2/943 ;
Abstract

A semiconductor device, such as a MOSFET or PN diode rectifier, has a p-n junction ( ) between a first device region ( ) and an underlying voltage-sustaining zone ( ). Trenched field-shaping regions ( ) extend through the voltage-sustaining zone ( ) to improve the voltage-blocking and on-resistance characteristics of the device. The trenched field-shaping region ( ) comprises a resistive path ( ) accommodated in a trench ( ) that has an insulating layer ( ) at its side-walls. The insulating layer ( ) dielectrically couples potential from the resistive path ( ) to the voltage-sustaining zone ( ) that is depleted in a voltage-blocking mode of operation of the device. The insulating layer ( ) extends at the side-walls of the trench ( ) to an upper level ( ) that is higher than a lower level ( ) at which the resistive path ( ) starts in the trench ( ). This lower level ( ) is more closely aligned to the p-n junction ( ) and is protected by the insulating layer ( ) extending to the higher level ( ). This construction enables the electric field distribution in the voltage-sustaining zone ( ) to be improved by aligning very closely the start of the potential drop along the resistive path ( ) with the p-n junction depth (d).


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