The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2003
Filed:
Oct. 17, 2001
Young-Doo Yoo, Seoul, KR;
Hong-shin Jun, Seongnam, KR;
Abstract
A semiconductor device including a built-in redundancy analysis (BIRA) circuit for simultaneously testing and analyzing failures of a plurality of memories, and a failure analyzing method, includes a plurality of memory blocks, a plurality of built-in redundancy analysis units for outputting a group of failure repairing information signals by testing and analyzing a corresponding memory block among the plurality of memory blocks in response to common driving signals and each of independent selection signals, and a controller for generating the common driving signals and the respective independent selection signals in response to a plurality of externally applied control signals and sequentially receiving and sequentially outputting the group of failure repairing information signals generated from the respective built-in redundancy analysis units. According to the semiconductor device and the failure analyzing method, it is possible to reduce the test time and expense since a plurality of memories having different sizes can be simultaneously tested and analyzed.